In order to synthesize the VHDL model, you need to process the VHDL design with a number of programs. The typical necessary steps are mentioned in this section.
You need to open the synthesis tool and import all the required files. Better still, you might even be able to do it from within the command line.
The default project file is supplied for Synplify. You can find it in the directory $ROOTDIR/syn. You should be able to open it from within the Synplify development environment, and be free of errors.
It should now be possible to click on the Run button and start translation.
Changing targets: The project file is preset for the XSV Board model. In case you have another board to work with, you will have to review the synthesis parameters.
The translation should produce a file named $ROOTDIR/syn/xess-leon.edf. This is an EDIF file required as input to the Xilinx Design Manager.
The EDIF file that we created by using Synplify and the instructions from the previous section needs to be converted into a bitstream file (extension .BIT) in order to be downloaded onto the FPGA device.
The tool we used for the conversion is the Xilinx Design Manager from the Xilinx Foundation Tools.
The first step is invoking the Xilinx Design Manager either from the Start menu or from the command line.
Non-windows users note: You may find the startup method to be different for your system.
You should now open the Xilinx Design Manager project file. This file is distinguished by the extension .XPJ. A default project file is provided for Design Manager. This file contains all the necessary pieces of information fro successful bitstream generation. We are therefore describing the steps needed to use this file to obtain the FPGA bitstream.
Select the File->Open (Ctrl-O) option. A dialog box will appear offering possibility to either choose one of the available projects from the list or select an existing project that is not in the list.
From the Open dialog box, select the Browse option. Find the file by the name $ROOTDIR/syn/xproj/xess-leon.prj and open it.
To complete bitstream generation you need to select Design->Implement menu option and wait for the design manager to finish.
|If you decide to create a new project.|
Do not forget to include the right constraints file. It is used to make physical mapping from VHDL signal names to actual FPGA pins. You absoulutely need to have an appropriate constraints file.
A constraints file suitable for use in this example is provided as $ROOTDIR/syn/xess-BonPS2.ucf.
If you decide to use the Design Manager project file provided with the project, you need not worry about the constraints file as it is included automatically.
The bitstream generation process should yield a file named $ROOTDIR/syn/xess-leon.bit. This file contains encoded description of the FPGA logic configuration corresponding to the design we began with, and readable by the programmer utility.