Digital IC Design

Welcome to the course website! This website will be created and updated during the course.

News and Notes.

2011-06-17:
The exam of April 14 last, and its solutions, have been made available below.

NewsArchive for older news.

About the Course

This course will present a broad yet thorough overview of the subject of digital VLSI design, spanning both the circuit and the system abstractions. This complete picture is the only way to make the right tradeoffs, find the most suitable optimizations and the best implementation strategies for very large scale integrated circuits in deep-submicron technologies. After an introduction to technology, devices and interconnect, combinational logic gates and sequential elements are studied. This is followed by system level perspectives of implementation fabrics, interconnect issues, timing issues and the design of macro blocks. At each level, the opportunities and limitations of the physical implementation are considered for finding better solutions and tradeoffs. This includes the consequences of the analog behavior of digital systems with respect to e.g. cross-talk noise and signal waveforms, that generally tend to become more influential with each new technology generation.

The course will include a design project, using Cadence. The grade will be determined for 50% by the exam, and for 50% by the lab course (project) results. In addition, bonus points will be awarded to the teams with the best designs. See Project and slides.

Part 1 of the book (Chapters 1-4) is prerequisite knowledge, although we spent about 1 lecture and a half for review. Also, we will later in the course touch upon some of the topics of part 1. Subsequently, we will study from Chapters 5 through 11.

The exam material is as follows. This is the list of sections to be studied for the course year 2010-2011. Please also study all introductory and conclusion sections of the relevant chapters.

Chapter	Topic	Remarks
Ch 1	Intro	Completely, pay attention to § 1.3
Ch 2	Manufacturing	§ 2.1 - 2.3
Ch 3	Devices	Completely
Ch 4	Interconnect	§ 4.1 - 4.4.4
Ch 5	Inverter	Completely
Ch 6	Combinational	Completely
Ch 7	Sequential	§ 7.1 - 7.5.1
Ch 10	Timing	§ 10.1 - 10.3
Ch 11	Arithmetic	§ 11.1 - 11.3

A written exam will be held on April 14, 2011, from 9 am to 12 am.

The exam will be an open-book exam. You are allowed to have the Rabaey book with you. In addition, you may use a printed copy of the lecture slides, possibly with your own annotations. You are not allowed to consult any other material during the exam.

Practice exams from previous years: 2008, answers, 2009-a, answers, 2009-b, 2011-a, answers.

Collected exercises from the book: rabaey-exercises-collected.pdf.

Design Project

See Project for more information.

Slides

Here are the slides:

1up - 6up - Introduction to the course
1up - 6up - Devices (Chapter 3) (update 2011-02-10)
1up - 6up - Process (Chapter 2)
1up - 6up - Inverter (Chapter 5)
1up - 6up - Combinational Circuits (Chapter 6)
1up - 6up - Sequential (Clocked Storage) Elements (Chapter 7)
1up - 6up - Timing (Clocking) (Chapter 10)
1up - 6up - Interconnect (R, C, Delay) (Chapter 4)
1up - 6up - Modularity (Chapter 11)
1up - 6up - Instructions for Spectre and Virtuoso assignments
1up - 6up - Layout rules, for Assignment 2
1up - 6up - Instructions for Spectre and Virtuoso assignments
1up - 6up - Description of Project, updated Feb 19 (time to digital converter)
1up - 6up - Description of TDC Architectures

Assignment

Instructions and pointers to be found in Assignment