VLSI circuit level modeling and analysis

Physical modeling and analysis of VLSI circuits

Program leaders: Nick van der Meijs
Researchers: Michel Berkelaar, Amir Zjajo, Qin Tang, Yu Bi

Mission

How can we design, model and characterize VLSI systems and circuits, which may use uncommon techniques and operate in uncommon ranges? We aim to have available a complete trajectory of design and verification tools. Scientifically, we work on physical modeling, electrical and timing behavior analysis as well as simulation of large VLSI circuits, with an emphasis on variability. To enable this, we develop super-fast solvers for the resulting systems of equations, using our ideas from time-varying systems theory.

Research

SPACE

This research track has been ongoing for more than ten years now and has produced a major piece of software called SPACE, a layout-to-circuit extractor. We are still working hard at it and will continue to research a number of new and old problems connected to circuit extraction.

MODERN

The ever-decreasing feature sizes of CMOS technologies have lead to a growing impact of variability on the performance of ICs. The electrical properties of transistors and wires on a chip vary more and more with respect to what is expected, even on a single chip there are large differences between identically designed devices. To study the design and analysis of ICs under such large variability, we are a partner in the MODERN project, which is sponsored by the European Union ENIAC program.

COBRA

We are also a partner in the COBRA project. This project studies the problems which arise when we go from the traditional planar IC designs to 3D integration.

Jobs

• For the COBRA project we are looking for a Ph.D. student. The topic is PV-Aware Design for Reliable 3-D Integration. For more information see the full description. If you are interested in this position, please contact dr.ir. Michel Berkelaar.

Master's projects

Internal at TUD

There are always many opportunities to help in the group's research activities in the form of a Master's project. Please come and talk to us, and we can find the best fit for your interests and abilities. Some possible topics:

• 3D Boundary Element mesh generation (SPACE)
• VIA Farm modeling (SPACE)
• Develop a parameterized RLC model for interconnect (MODERN)
• Find a statistical model for crosstalk delay (MODERN)
• Investigate statistical delay behavior of complex CMOS cells like flip-flops, multiplexers... (MODERN)
• PULSAR navigation blocks and modules
• Sensing and Interface circuits for dynamic PVT aware computing arrays (COBRA)

External

Our research partners sometimes offer the possibility of Master's projects performed at their site. Currently available:

• Low power design methodology improvement at NXP.
• Predictability improvement for RF designs at NXP.
• Design of substrate noise sensor at NXP.

If you are interested in one of these projects, please contact dr.ir. Michel Berkelaar.

|  April 29, 2011   |