VLSI system design and automation

Program leader: Rene van Leuken
Researchers: Alexander de Graaf, Huib Lincklaen-Arriens, Alejandro Viteri
PhD students: Sumeet Kumar, Tao Xu, Mu Zhou
MSc students: Tom v Leeuwen, Pim Tamerus, Harry Broeders, Marta Guide, Arnica Aggarwal, Radhika Japtap, Ren Xianli, Mesfin Gashaw, Chris Feenstra, Yi Guanyu (IMEC), Kezheng Ma (Holst)

Mission

The aim of the group is two fold. First, we want to investigate, understand, enhance and enable a trajectory (design flow), that will facilitate a performance conscience methodology to realize digital systems starting from high level descriptions of algorithms. Secondly we want to use this methodology to realize typical DSP computing blocks, for example wireless communication - or wireless sensor node functions or similar compute blocks.

Research

This research field has a long history; It started in the early 90's and after a long period of 'invisibility' has become again a prominent research topic. Major issues include the 'compilation' of high level language descriptions into of set of signal flow graphs, 'optimization' of these graphs, followed by well knows steps as scheduling, mapping, binding and state machine generation. The major challenges are in the first two steps: compilation and optimization. Several languages have been developed over the years to support a designer in these tasks. Most prominent is VHDL and more recently SystemC has emerged. Those languages provide a syntax; How to use such a language in an efficient way is an important research topic. In other words, computer languages exist which help the designer to describe his 'system'. This designer has to make choices between different architectural solutions, different partitions, etc. Typically he is concerned about speed, power, and area. How to find a solution which fulfills his requirements? This is the research topic we want to address.

Projects

COBRA: Computing Fabric for high performance Applications [2010-2013]

Hardwired SoC architectures suffer from a lack of flexibility regarding market evolution, resulting in an excessive design cycle time and increased cost. Furthermore, process variability is not yet well addressed for 32 nm and beyond. The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous hardware/software sub-systems by a regular array of processors. The platform will be driven by Telecom, Video and Multimedia benchmark applications and demonstrated on 32nm silicon with 3D stacking.

The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous mixed HW/SW specialized sub-systems by an application specific processor array. This massively parallel computing fabric will also improve manufacturability and energy efficiency of new Systems On Chip, due to its design regularity, while at the same time maximising flexibility by allowing software product derivatives to be generated. Software product derivatives will reduce development and manufacturing costs as well as Time-to-market when compared with hardwired alternatives.

FASTCOM: Fast wireless network for sensor communication within a lithography machine [2010-2013]

Fast wireless network for sensor communication within a lithography machine [2010-2013] Lithography machines have a fast-moving waferstage; also the mask is moving. These stages have many sensors used for accurate positioning. It is desired to connect these sensors wirelessly to a central controller. However, the aggregate data rate is very high (over 1 Gbps), and the latency requirements are very tight. Currently, there are no wireless standards that can accomodate this.

BDREAMS: Beyond DREAMS (Development of a Virtual Prototyping Environment for multi-radio and cognitive radio) [2009-2011]

Beyond DREAMS will provide methods to handle the complexity and shorten the path from specification to implementation of future analogue mixed signal Systems on Chip / Systems in Packages / Hardware / Software and in heterogeneous systems (mechanical, optical, etc.). Extensions for AMS modelling and simulation will be issued in the SoC domain standards: SystemC and IP-XACT via the Standardization bodies OSCI and ACCELLERA. Demonstrators based on industrial test cases will be developed. Consortium is rich of leaders in AMS design domain: three semiconductor companies, a major equipment supplier, research institutes and universities.

Upcoming products of Europe's semiconductor companies more and more interact directly with their analogue physical environment. This leads to a new quality of System on Chip (SoC) and System in Package (SiP) products that combine digital Hardware and software (HW/SW) systems with analogue and mixed-signal blocks such as radio frequency (RF) interfaces, power electronics, or sensors and actuators. In such SoC or SiP, HW/SW systems, often implemented using intellectual property (IP) cores and complex software systems, are tightly interwoven with analogue (RF, power ...) modules. We call such systems Embedded Analogue and Mixed-Signal Systems (EAMS) to underline the new and common complexity that arises by mixing digital HW/SW systems with analogue/RF systems in a SoC or SiP. A common challenge for the development of EAMS is to cope with the digital HW/SW system, and at the same time to understand its environment (e.g. network protocol, traffic, sensor, RF circuits).

Recently Ended Projects

TARDIS [EU IST cluster project, 1997-2002]

This was a European cluster project (for dissemination of research results) with 50 parters from industry and universities, of which we carry the coordination. It is aimed at fostering excellence in microelectronics design skills, and bringing those skills to broad industrial use. It consists of sub-clusters for Low Power Design (LPD: design methods for reducing the power consumption of electronic circuits) and Mixed Signal Design (MSD: design methods for solving problems related to the integration of analog and digital functions on a single semiconductor device).

MARLOW [EU IST Network of Excellence, 2002-2005]

This EU IST cluster project is the follow-up of TARDIS, and will create a flexible and dynamic framework that will favor the exchange of information and the transfer of technology among the partners and with industry and SMEs. Services that will be provided include, but are not limited to a comprehensive low-power design WEB-portal, a technology and methodology roadmap giving directions for future challenging areas of research and development, on-demand consulting and points of technical synchronization for the low-power design community.

|  28 October 2010   |