Signal Processing for reduced hardware massive MIMO
Topic: Explore hardware architectures and signal processing concepts to estimate the wireless channel, track users and reconstruct signals with reduced dimension hardware
Massive arrays are expected to be a key component in next generation of wireless communications due to its increased spectral efficiency and throughputs. However, introduction of multiple antennas increases the cost and complexity of the massive MIMO. The signals at closely spaced antenna elements might be significantly correlated, due to RF impairments, antenna coupling, etc. The overall project is to jointly explore hardware architectures and novel signal processing concepts to estimate the wireless channel, track users and reconstruct signals with reduced dimension hardware.
Project outside the universityAlcatel-Lucent (Dublin, Ireland)
- F. Rusek, D. Persson, B. K. Lau, E. Larsson, T. Marzetta, O. Edfors, F. Tufvesson, "Scaling Up MIMO: Opportunities and Challenges with Very Large Arrays," Signal Processing Magazine, IEEE , vol.30, no.1, pp.40-60, Jan. 2013
- J. Hoydis, S. ten Brink, M. Debbah, "Massive MIMO in the UL/DL of Cellular Networks: How Many Antennas Do We Need?," Selected Areas in Communications, IEEE Journal on , vol.31, no.2, pp.160-171, February 2013
- H. Q. Ngo, E. G. Larsson, and T. L. Marzetta, “The multicell multiuser MIMO uplink with very large antenna arrays and a finite-dimensional channel,” IEEE Transactions on Communications, vol. 61, no. 6, pp. 2350–2361, 2013.
AssignmentThe aim of the MSc thesis is to propose signal processing algorithms for reduced complexity hardware and evaluate their performance. This work can be used as a starting point to propose efficient massive MIMO wireless access strategies for reduced complexity hardware.
RequirementsThe student is expected to be strong in Linear Algebra and Signal Processing. Knowledge of Massive MIMO and wireless propagation is a plus.
Additional information: contact email@example.com
prof.dr.ir. Alle-Jan van der Veen
Circuits and Systems Group
Department of Microelectronics
Last modified: 2015-03-27