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Circuits and Systems

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ET 4351 VLSI systems on chip

Information

Instructors

dr.ir. Rene van Leuken (27) 86696

ECTS credits 4

Literature

Understanding Behavioral Synthesis, A practical Guide to High-Level Design, John P. Elliot, Kluwer
Digital Systems Design with VHDL and Synthesis: An Integrated Approach, by K.C. Chang , Publisher: Wiley, ISBN: 0769500234
Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, by Erik Brunvand, Addison-Wesley, ISBN-10: 0321547993

Hours per week

20 hours lectures and 20 hours lab work

Assessment

Design report

Goals

The aim of the course is to address some important aspects of Systems on Chip (SoC) design: Including: 1) Algorithm to specification 2) Low power digital design issues, 3) On-chip system IP high level interconnect issues, 4) Hardware and software interaction issues

Detailed description of topics

In this course, we venture to design a system on chip, where large IP blocks are available. The design problem to be solved is how to design, connect and implement these large macro IP blocks, in the ‘best’ possible way, i.e. in terms of speed, bandwidth, power consumption and data reliability. Topics covered among other low power optimization and reduction techniques, SoC design methodology, modeling, specification and implementation, communication architecture and protocols. Modern design starts from a C-based description (System-C) or behavior description through synthesis tools to an FPGA implementation. This course will introduce the SystemC language, SystemC-AMS and SystemC-TLM. High level modeling concepts using VHDL will be presented, as well as an introduction to synthesizable VHDL and loop optimization. This year we will include an ASIC (semi-custom) design flow.

The lectures are mainly a general introduction and include a discussion and demonstration of the design tools. The students will start using the tools by means of a well-defined student design project that uses part (or all) of the design path. Some digital circuits (basic structures) are being studied as examples.

Schedule 2012

The course will be given in the fourth quarter and will be taught in English. The schedule is as follows:

Tue. Apr. 24

(RvL)

Introduction

Fri. Apr. 27

(RvL)

Introduction VHDL, synthesizable VHDL, behavioral synthesis, Structured VHDL design

Tue. May. 8

(RvL)

Communication (Wishbone and OPB Bus)

Fri. May. 11

(AcdG,RvL)

Introduction into SystemC, some basic C++, SystemC examples

Tue. May. 15

(RvL)

Low Power design (circuit level design: clock and communication optimization)

Tue. May. 22

(AcdG,RvL)

SystemC AMS and TLM

Fri. May 25

(AcdG,RvL)

Introduction to ASIC design flow (Synopsys DC and Cadence SOCE)

Tue. May 29

(RvL)

The introduction & division of the design projects topics (Image,Ethernet and ASIC) and a demonstration of an example design project

Fri. Jun 1

Optional (depends on # students)

ASIC design teams meeting (only). Location H17.150

Contact and Location

René van Leuken
Email adress: t.g.r.m.vanleuken (at) tudelft.nl
Tel. number: +31 (15) 278 6696
Secretariat: Mrs. Minaksie Ramsoekh, Rm. 17.230, tel. 81372

Course location:
(Tuesday, 5+6) 24/4/12, 8/5/12, 15/5/12, 22/5/12, 29/5/12 (13.45 hours)
Faculty TN-CZ E (F005), Building 22
Room E

(Friday, 1+2) 27/4/12, 11/5/12, 25/5/12 (8.45 hours)
Faculty CT-CZ F, Building 23
Room F

Master of Science Projects

SoC VHDL/ASIC/FPGA and EDA projects: to conceive, develop, implement and experimentally validate innovative electronic systems

Handouts and Documents (Updated 10/04/2012)

Lecture 1, introduction

Lecture 2, A VHDL introduction , Meet Synthesizable VHDL , Structured VHDL design methods and Loops in VHDL.

A Zip file with a number of examples of loops in VHDL.

Lecture 3, Communication, Set 1 , NoC , OPB , and VHDL example .

Other materials:
Wishbone Bus specification
Amba Bus specification
IBM OPB specification
OPB tutorial
OPB uart example

Lecture 4, Low Power Design. Set 1, Introduction , and Set 2, Optimization
Other materials:
Paper on Power-Aware Clock Tree Planning

Lecture 5, SystemC.

Lecture 6, SystemC AMS and SystemC TLM.

Lecture 7, Asic flow

Reader (local access only, i.e. 130.161.. and 131.180.. and 145.94..)

Engineering the Complex SOC: Fast, Flexible Design with Configurable Processors Chris Rowen, Steve Leibson. chapter 3. A new look at SOC design
Embedded System Design: A Unified Hardware/Software Approach, Frank Vahid and Tony Givargis, Chapter 4.
The Design Warrier's Guide to FPGA, Clive Maxfield, Chapter 9, Design flows
Networks on Chip, Energy reliability trade-offs for NoCs, Davide Bertozzi, Luca Benini, Giovanni De Micheli
Low Power Electronics Design VHDL for Low Power, Amara Amara and Philippe Royannez
Writing VHDL for RTL Stephen Edwards
A structured VHDL design method
Chapter 6. LOOPS. Understanding Behavioral Synthesis, A practical Guide to High-Level Design, John P. Elliot, Kluwer

Cadence CtoS User Guide

Example Code

VHDL Examples

The Design Project

You'll perform a design-it-yourself project in the second half of the class.

There are 4 deliverables for the project:

A short project proposal describing in broad terms what you plan to build and how you plan to build it
A detailed project design describing in detail the architecture of your project, both hardware and software. This should include block diagrams, memory maps, lists of registers: everything someone else would need to understand your design. You should have done some preliminary implementation work by this point to validate your design.
A demo of your project.
A final project report.

The Design Report

Include the following sections:

An overview of your project: description of your project. (Name,Number/what/how/results)
A) In the case of the IMAGE or IO communication design project. The detailed project design documents: the architecture description of your project, both hardware and software. This should include block diagrams, memory maps, lists of registers: everything someone else would need to understand your design. A dump of the wave/signals of your simulator window of the critical signals of your design. And proof that your project is synthesizable; E.g. by providing a schematic generated by Synplify or Xilinx XST or Design Vision or Cadence CtoS in the case of SystemC.

B) In the case of the ASIC design project. The detailed project design documents: the design description of your project, including the major design steps: area, timing and power analyzes, IO placement, power planning, floorplanning, clock generation and place & route. Everything someone else would need to understand your design steps. A dump of the wave/signals of your simulator window of the critical signals of your design for each design step: before and after synthesis, after place&route.
In case a multi person project: A section listing who did what and what lessons you learned and advice for future projects
A) In the case of the IMAGE or IO communication design project. Complete listings of every file you wrote for the project. Include C source, synthesizable behavior VHDL source, and things such as .mhs and .io files. Don't include any file that was generated automatically.

B) In the case of the ASIC design project: Include the following directories in a single zip file: HDL, PAR/CONF, PAR/RPT, PAR/CTS, SYN/RPT, the .io file and any tcl file you may have changed.

Include all your text in a single .pdf file (don't print it out) and email it to me.

Also create a .tar.gz or zip file that just includes the files necessary (i.e as indicated above) to build your project. Also email this to me.

The Lab: computers, EDA software, FPGA's

The Lab is located on the 16th floor, room H16.090. Twelve computers are available; All have installed the required (Modelsim,Xilinx, Synopsys and Cadence) software you need for the design and implementation of your project. For those students that have selected an IO Communication project FPGA development and debug equipment is available on the 17th floor, room H17.240. This room is open 9 to 5 and is available on appointment only. Before you can use the FPGA development and debug equipment you need to have a 'correct' simulation result of your design.

Design Projects

Project 1: ASIC design
Note: There will be a special meeting on June 1th.
info files in zip format (updated 06/09/2010)
ASIC design FAQ
Project 2: Image co-processor
Note: You should choose one of the (or more if you want) threshold algorithms, (e,k,m,o). You CAN NOT select the binarize algorithm (for the obvious reason).

info files in zip format (updated 17/02/2009)
Project 3: IO communication processor
Ethernet info files in zip format (updated 06/09/2010)

What else do you need

The 2012 project assigments: a PDF file.

   Download the Top-down digital design flow (EDA tools: Mentor Modelsim, Synopsys Design Compiler, Cadence SoC Encounter):a PDF file (2011).

Download the 'VHDL Simulation Package': a zip file.
   Download the VHDL Simulation Package User Guide: a PDF file.

Download the additional 'VHDL MB-Lite Package': a zip file.
   Download the MB-Lite to FPGA (Project 3) User Guide: a PDF file.

Download the 'SystemC Simulation Package': a zip file.
   Download the SystemC Simulation Package User Guide: a PDF file.

How to use the CTOS email batch interface. Zip file including example code, tcl files and README.

CTOS User Guide section 14.12 which describes SystemC restrictions. Read chapter 14 to find-out about all limitations. The complete User Guide can be downloaded from the Reader (above).

User Guide Avnet Spartan3 FPGA board
Wishbone Bus specification
Using Synplify Pro, ISE and ModelSim Introduction into the usage of these tools and the source files.

MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture

Deadline Submission Design Report

Design Reports should be submitted before Sunday July 1, 2012! In week 27 (July 2-6) evaluation and grading will take place. This means that you will receive your course grade before July 7.

If you can not finish your project before July 1, you can submit your design report before the first week of October 2012. (I.e. you can submit a design report every 3 months).